1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a multi-bit parallel test of semiconductor memory device.
2. Description of the Related Art
In general, a semiconductor memory device such as DRAM supports a variety of test items, and a variety of tests are performed at a wafer level and a package level to reduce the manufacturing cost and improve the yield. In particular, a multi-bit parallel test (hereafter, referred to as a parallel test) is an important test for reducing the test time and is performed at both a wafer level and a package level.
In the technology for testing a semiconductor memory device, it is not only important to perform a reliable test, but also it is essential to perform a test at a high speed. In particular, whether the development time and the test time of a semiconductor memory device can be reduced or not has an effect on a manufacturing cost. Therefore, the reduction of the test time has become an important issue in the efficiency of production and the competition between makers. In the conventional semiconductor memory device, a test was performed for each memory cell to determine whether the memory cell is passed or failed at a wafer level and a package level. Therefore, with the high integration of the semiconductor memory device, the test time has proportionally increased. Accordingly, the parallel test has been introduced to reduce the test time.
The operation of the parallel test will be briefly described. First, the same data are written into a plurality of cells, and an exclusive OR gate is then used to read the data during a read operation. When the same data are read from the plurality of cells, ‘1’ is outputted to make a pass decision, and when different data is read from any one of the plurality of cells, ‘0’ is outputted to make a fail decision. In such a parallel test, the test is not performed for each memory cell, but a large number of banks are simultaneously enabled at a time to perform a write/read operation of data. Therefore, it may be possible to reduce the test time.
Recently, the arrangement of segment input/output (SIO) lines has been achieved by considering optimization for the architecture or layout of memory cell arrays, bit line sense amplifiers (BLSA), bit lines and the like. In other words, a plurality of write data provided from different write driving circuits are alternately loaded into a plurality of segment input/output lines.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, a plurality of first segment input/output lines SIO0 to SIO3 and a plurality of second segment input/output lines SIO4 to SIO7, coupled to a memory cell array area CA, are alternately arranged. Furthermore, the plurality of first segment input/output lines SIO0 to SIO3 are connected to a first write driving circuit 10 through a plurality of first local input/output lines LIO0 to LIO3, and the plurality of second segment input/output lines SIO4 to SIO7 are connected to a second write driving circuit 20 through a plurality of second local input/output lines LIO4 to LIO7.
Here, the first write driving circuit 10 loads a plurality of first write data loaded in a plurality of first global input/output lines GIO<0:3> into the plurality of first local input/output lines LIO0 to LIO3 in response to a first write enable signal BWEN03. The second write driving circuit 20 loads a plurality of second write data loaded in a plurality of second global input/output lines GIO<4:7> into the plurality of second local input/output lines LIO4 to LIO7 in response to a second write enable signal BWEN47. At this time, the first and second write driving circuit 10 and 20 are selectively enabled based on a data width option mode X8 or X4. For example, any one of the first and second write driving circuits 10 and 20 is enabled in the X4 mode, and both of the first and second write driving circuits 10 and 20 are enabled in the X8 mode.
However, the semiconductor memory device having the above-described configuration has the following concerns during the parallel test mode.
The parallel test mode is performed in response to a data width option mode having a maximum data width among the data width option modes supported by the semiconductor memory device. For example, when the X8 mode and the X4 mode are supported as the data width option modes, the parallel test mode is performed under the condition of the X8 mode.
However, since the first and second write driving circuits 10 and 20 are controlled to be enabled based on the data width option mode X8 or X4 during a write operation, and the write operation is performed in a different environment condition depending on the data width option mode X8 or X4. In the X4 mode, only the first write driving circuit 10 is enabled to load the plurality of first write data loaded in the plurality of first global input/output lines GIO<0:3> into the plurality of first local input/output lines LIO0 to LIO3, and the plurality of first write data are finally written into the memory cell array CA through the plurality of first segment input/output lines SIO0 to SIO3 connected to the plurality of first local input/output lines LIO0 to LIO3. At this time, since a column select signal YI is activated, charge sharing occurs in the plurality of second segment input/output lines SIO4 to SIO7 connected to the disabled second write driving circuit 20. In such a case, as the plurality of first write data are driven to the plurality of first segment input/output lines SIO0 to SIO3 as illustrated in FIG. 2, the plurality of first write data may have a coupling effect on an arbitrary second segment input/output line (for example, SIO6). In a serious case, amplified data of a BLSA (not illustrated) may be inverted to cause a read failure.
Therefore, the conventional semiconductor memory device does not reflect a coupling effect, which occurs in an arbitrary segment input/output line (for example, SIO6) in a specific data width option mode (for example, X4 mode), during the parallel test mode. Therefore, the screen ability of the semiconductor memory device may decrease.